1. Field of the Invention
The present invention relates to a barrel shift circuit for simultaneously shifting a plurality of parallel signals, and more particularly to such a circuit capable of executing a logical shift or an arithmetical shift in leftward and rightward directions.
2. Description of Related Art
In logical and arithmetical operations, the data or numerals consisting of a plurality of bits are frequently shifted. For such a shift operation, there has been heretofore used a barrel shift circuit as shown in FIG. 1. The barrel shift circuit shown is a cyclic shift type of four bit barrel shift circuit having four parallel input lines 1a, 1b, 1c and 1d, which are in turn connected to four corresponding parallel output lines 2a, 2b, 2c and 2d through field effect transistors (hereinafter abbreviated to "FETs") Q.sub.1 and Q.sub.9, Q.sub.3 and Q.sub.11, Q.sub.5, and Q.sub.13, and Q.sub.7 and Q.sub.15. Furthermore, the input lines 1a, 1b, 1c and 1d are respectively connected through FETs Q.sub.6, Q.sub.8, Q.sub.2 and Q.sub.4 to the output terminals of the FETs Q.sub.5, Q.sub.7, Q.sub.1 and Q.sub.3 cyclically leftwardly shifted by two lines (bits), respectively. Also, the output terminals of the FETs Q.sub.1, Q.sub.3, Q.sub.5 and Q.sub.7 are connected through FETs Q.sub.12, Q.sub.14, Q.sub.16 and Q.sub.10 to the output lines cyclically leftwardly shifted by one line (bit). A shift number control line 3 is connected through an inverter 4 commonly to the gates of the FETs Q.sub.1, Q.sub.3, Q.sub.5 and Q.sub.7 and also directly in common to the gates of the FETs Q.sub.2, Q.sub.4, Q.sub.6 and Q.sub.8. Another shift number control line 5 is connected through another inverter 6 to the gates of the FETs Q.sub.9, Q.sub.11, Q.sub.13 and Q.sub.15 and directly to the gates of the FETs Q.sub.10, Q.sub.12, Q.sub.14 and Q.sub.16.
With the above arrangement, if the data of four bits inputted through the input lines 1a-1b are to be shifted leftwardly by one bit, logical control signals "0" and "1" are applied to the control lines 3 and 5, respectively. Consequently, the FETs Q.sub.1, Q.sub.3, Q.sub.5 and Q.sub.7 are turned on and the FETs Q.sub.2, Q.sub.4, Q.sub.6 and Q.sub.8 are maintained in the off condition. In addition, the FETs Q.sub.9, Q.sub.11, Q.sub.13 and Q.sub.15 are in the off condition and the FETs Q.sub.10, Q.sub.12, Q.sub.14 and Q.sub.16 are turned on. Therefore, the input line 1a is connected through the FETs Q.sub.1 and Q.sub.12 to the output line 2b, the input line 1b is connected through Q.sub.3 and Q.sub.14 to the output line 2c, and similarly, the inputs 1c and 1d are connected to the outputs 2d and 2a, respectively.
As a result, assuming that the input line 1a is the least significant bit and the input line 1d is the most significant bit, the most significant bit is transferred to the least significant bit, and the other input bits are shifted leftwardly by one bit. Namely, the inputted data is cyclically shifted leftwardly by one bit.
In addition, for a two bit shift, logical signals "1" and "0" are applied to the control lines 3 and 5, respectively, and for a three bit shift, a logical signal "1" is applied to both the control lines 3 and 5.
The barrel shift circuit shown in FIG. 1 can shift the inputted data leftwardly as mentioned above. However, in order to execute a rightward shift, there has been required another barrel shift circuit different from that shown in FIG. 1. In addition, each bit signal of the inputted data has to be passed through two FETs in the case of the four bit barrel shift circuit shown in FIG. 1 and also through n FETs (where n is positive integer) in the case of a 2.sup.n bit barrel shift circuit constructed similarly to the circuit of FIG. 1. Therefore, as the data length becomes longer, a longer time is required from the moment the data is inputted to the barrel shift circuit to the moment the shifted data is outputted from the barrel shift circuit. In other words, the barrel shift circuit is not suitable for processing data of a large bit number at a high speed.
For the purpose of eliminating this problem, there has been proposed another barrel shift circuit as shown in FIG. 2. The circuit shown comprises a barrel shift matrix 7 connected between four parallel input lines 8a, 8b, 8c and 8d and four parallel output lines 9a, 9b, 9c and 9d. The barrel shift matrix 7 includes FETs Q.sub.17 to Q.sub.32 arranged in the form of a matrix consisting of four rows and four columns. The FETs Q.sub.17, Q.sub.21, Q.sub.25 and Q.sub.29 n the rightmost or first column are connected at one end thereof to the first or least significant bit input line 8a. The FETs Q.sub.18, Q.sub.22, Q.sub.26 and Q.sub.30 in the second column are connected at one end thereof to the second input line 8b, the FETs in the third column to the third line 8c, and the FETs in the fourth or leftmost column to the fourth or most significant bit line 8d. Furthermore, the FETs Q.sub.17 to Q.sub.20 in the uppermost or first row are connected at the other end thereof to the corresponding output lines 9a to 9b, respectively. The FETs Q.sub.21 to Q.sub.24 in the second row are respectively connected at the other end thereof to the output lines 9b, 9c, 9d and 9a of columns cyclically shifted leftwardly by one column from the columns in which the FETs Q.sub.21 to Q.sub.24 are located. Similarly, the FETs Q.sub.25 to Q.sub.28 are connected at the other end thereof to the output lines 9c, 9d, 9 a and 9b, respectively, for a cyclical left shift of two bits, and the FETs Q.sub.29 to Q.sub.32 are connected at the other end thereof to the output lines 9d, 9a, 9b and 9d, respectively, for a three bit cyclical left shift. All the FETs in each row have gates connected in common so that the FETs in the same row are simultaneously turned on and off by a shift number controller 10, which is in turn connected with shift number control lines 11 and 12. This shift number controller has two inverters 13 connected to the control lines 11 and 12 and four two-input NOR gates 14, 15, 16 and 17 whose outputs are connected to the gates of the FETs in the respective rows of the matrix 7, as shown in FIG. 1, so that the shift number signal supplied through the two control lines 11 and 12 is decoded to turn on all the FETs in the selected one of the four rows.
Now, if a leftward shift of one bit should be executed, logical signals "1" and "0" are inputted through the control lines 11 and 12, respectively. In response to such a shift number control signal, the controller 10 outputs the logical signal "1" from the NOR gate 15 and the logical signal "0" from the other NOR gates 14, 16, and 17. Therefore, the FETs Q.sub.21 to Q.sub.24 in the second column are turned on, and all the other FETs are maintained in the off condition. As a result, the input lines 8a, 8b, 8c and 8d are connected to the output lines 9b, 9c, 9d and 9a, respectively, so that the inputted data shifted cyclically leftwardly by one bit.
In the barrel shift circuit as shown in FIG. 2, each bit signal of the inputted data is shifted and outputted by passing through only one FET. In other words, if a barrel shift circuit is constructed in accordance with the manner shown in FIG. 2, even if the data length to be processed is made longer, it is possible to shift the inputted data at a high speed since the inputted data passes through only one FET between the input and the output of the barrel shift circuit. However, again, a different barrel shift matrix circuit is required for a rightward shift, and therefore, the barrel shift circuit was inevitably of large scale.
In view of the above and in order to perform bidirectional barrel shift by means of only one barrel shift matrix, there has been proposed to locate a complement generator 31 before the shift number controller 10 as shown in dotted lines in FIG. 2.
in a cyclic shift operation, data of 2.sup.m bits (where m=positive integer) shifted rightwardly n bits (where n=positive integer) is equivalent to the same data shifted leftwardly by the bit number corresponding to the 1's complement of the decimal number n (the complement of n in binary notation). For example, assuming that data of four bits "X.sub.3 X.sub.2 X.sub.1 X.sub.0 " are shifted rightwardly by three bits, the shifted data is represented by "X.sub.2 X.sub.1 X.sub.0 X.sub.3 ". On the other hand, the decimal number "3" is "11" in binary notation, and the complement of the binary number "11" is "01" which corresponds to the decimal number "1". Therefore, if the data "X.sub.3 X.sub.2 X.sub.1 X.sub.0 " is shifted leftwardly by one bit, the shifted data is "X.sub.2 X.sub.1 X.sub.0 X.sub.3 ", which is equivalent to the three bit rightwardly shifted data.
The complement generator 18 shown in FIG. 2 is operable to execute the above operation in response to a shift direction signal supplied to a control input 19 of the generator 18. Namely, when the shift direction signal indicates a left shift, the generator 18 output the shift number signal applied through input terminals 20 and 21, without any modification to the lines 11 and 12, respectively. On the other hand, when the shift direction signal requests a right shift, the generator 18 operates to calculate the 1's complement of the shift number signal applied through the input terminals 20 and 21, and then to supply the calculated complement to the lines 11 and 12.
In order to perform the above function, the complement generator 18 is mainly composed of inverters for inverting the inputted shift number signal of binary code and an adder for adding the binary number "1" to the inverted shift number signal of binary code. Therefore, the generator 18 requires a substantial number of elements and accordingly will inevitably be of large size.
As seen from the above, the barrel shift circuit incorporating the complement generator as shown in FIG. 2 can execute bidirectional barrel shift using only one barrel shift matrix. However, since the circuit requires an associated control circuit of a relatively large size, the barrel shift circuit is still large. In addition, it is not possible to execute a non-cyclic bidirectional barrel shift.